Term
| Arithmetic and logic unit (ALU) |
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Definition
| processor component, performs the computers data processing functions |
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Term
| Central processing unit (CPU) |
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Definition
| controls operation of the computer forms its data processing functions |
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Term
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Definition
| refers to the attributes of a system visible to a programmer or that have a direct impact on the logical execution of a program |
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Term
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Definition
| refers to the operational units and their interconnections that realize the architectural specifications |
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Definition
| processor component, provides internal storage to the CPU |
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Term
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Definition
| component which allows communication among the CPU, main memory, and I/O |
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Term
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Definition
| Contains the address of the next instruction pair to be fetched from memory |
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Term
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Definition
| A chip that contains all the components of a CPU |
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Term
| Memory buffer register (MBR) |
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Definition
| Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or the I/O unit |
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Term
| Memory address register (MAR) |
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Definition
| Specifies the address in memory of the word to be written from or read into the MBR |
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Term
| Instruction register (IR) |
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Definition
| Contains the opcode instruction being executed |
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Term
| Instruction buffer register (IBR) |
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Definition
| Used to hold temporarily the right-hand instruction from a word in memory |
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Term
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Definition
| The opcode of the next instruction is loaded into the IR and the address portion is loaded into MAR |
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Term
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Definition
| Control circuitry interprets the opcode and executes the instruction by sending out the appropriate control signals to cause data to be moved or an operation to be performed by the ALU |
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Term
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Definition
| Employed to hold temporarily operands and results of ALU operations |
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Term
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Definition
| The occurrence of events on the bus is determined by a clock |
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Term
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Definition
| Used to designate the source or destination of the data on the data bus |
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Term
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Definition
| The occurrence of one event on a bus follows and depends on the currents of a previous event |
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Term
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Definition
| Designating one device, processor or I/O module, as master of the bus |
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Term
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Definition
| the number of separate lines of the data bus |
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Term
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Definition
| A single hardware device responsible for allocating time on the bus |
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Term
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Definition
| Provides paths for moving data among system modules |
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Term
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Definition
| Each module contains access control logic and the modules act together to share the bus |
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Term
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Definition
| A mechanism by which other modules may interrupt the normal processing of the processor |
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Term
| Peripheral component interconnect (PCI) |
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Definition
| A high bandwidth, processor independent bus that can function as a as a mezzanine or peripheral bus |
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Term
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Definition
| time to perform read/write operation |
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Term
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Definition
| smaller, faster, more expensive memory are supplemented by larger, slower memories |
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Term
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Definition
| memory references by processor tend to cluster |
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Term
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Definition
| all write operations are made to main memory and cache |
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Term
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Definition
| updates are made only in the cache and a dirty/use bit is used to determine when a block is to be returned to main memory |
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Term
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Definition
| same as logical cache, stores data using virtual addresses |
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Term
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Definition
| instructions and data share the entire cache |
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Term
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Definition
| identifies which block is currently being stored |
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Term
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Definition
| half of cache devoted to instructions and the other to data |
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Term
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Definition
| cache consists of a number of sets which are in turn composed a number of lines |
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Term
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Definition
| when a new block is brought into a full cache, it replaces an existing block |
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Term
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Definition
| stores data using physical addresses in main memory |
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Term
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Definition
| same as virtual cache, stores data using virtual addresses |
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Term
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Definition
| each block of main memory maps to only one possible line of cache |
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Term
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Definition
| line in cache which stores a block from main memory |
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Term
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Definition
| each block of main memory can be mapped to any line of cache |
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Term
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Definition
| if accessed word is found in cache |
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Term
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Definition
| smallest and fastest memory available for a memory system |
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Term
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Definition
| if accessed word is not found in main memory |
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Term
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Definition
| accesses are not linear (disk) |
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Term
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Definition
| fraction of all accesses that are found in cache |
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Term
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Definition
| accesses are constant (main memory) |
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Term
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Definition
| accesses in a specific linear order (tape) |
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Term
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Definition
| tendency of execution to involve a number of clustered memory locations |
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Term
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Definition
| tendency of processor to access recently used memory locations |
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Term
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Definition
| holds information as long as power supplied |
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Term
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Definition
| uses same logic elements used in processor |
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Term
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Definition
| contains permanent pattern of data that cannot be changed |
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Term
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Definition
| read operations are performed more often than writing |
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Term
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Definition
| writing is performed electrically by supplier or customer |
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Term
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Definition
| holds information even when power is not supplied |
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Term
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Definition
| memory which uses block erasure |
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Term
| erasable programmable ROM (EPROM) |
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Definition
| read and written electrically and writing can done frequently but all data must be erased first |
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Term
| electrically erasable programmable ROM (EEPROM) |
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Definition
| read and written electrically and writing is done by update |
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Term
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Definition
| made with cells that store data as a charge on capacitors |
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Term
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Definition
| permanent physical defect that prevents memory cells from being reliable |
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Term
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Definition
| nondestructive event which alters the contents of a memory cell |
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Term
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Definition
| DRAM which is synchronized with a clock |
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Term
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Definition
seek time and rotational delay
Ta = Ts + 1/2r + b/rN |
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Term
| constant angular velocity (CAV) |
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Definition
| disk has same number of sectors on each track |
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Term
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Definition
| space which separates tracks on disk |
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Term
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Definition
| has more sectors on outside than inside |
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Term
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Definition
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Term
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Definition
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Term
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Definition
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Term
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Definition
| bit-interleaved parity, reduced mode |
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Term
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Definition
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Term
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Definition
| block-interleaved distributed parity, eliminates parity bottleneck |
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Term
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Definition
| block interleaved double distributed |
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Term
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Definition
| time for beginning of sector to reach head |
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Term
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Definition
| data sections usually 512 bytes each |
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Term
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Definition
| time to position head over track |
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Term
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Definition
| concentric set rings on disk |
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Term
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Definition
time to transfer data
T = b/rN |
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