Term
| ARITHMETIC LOGIC UNIT (ALU) |
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Definition
| A CPU COMPONENT THAT PERFORMS MATHEMATICAL FUNCTIONS ON DATA SOTRED IN THE REGISTER AREA |
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Term
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Definition
| A LOW-LEVEL LANGUAGE IN WHICH A CPU'S INSTRUCTION SET IS WRITTEN |
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Definition
| THE NETWORK CIRCUITRY THAT CONNECTS ALL THE OTHER MAJOR COMPONETS TOGETHER, ACCEPT DATA, AND SENDS DATA THROUGH THE INPUT AND OUTPUT BUS SECTIONS |
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Definition
| A SMALL TEMPORARY MEMORY AREA THAT IS USED TO SEPARATE AND STORE INCOMING DATA AND INSTRUCTIONS |
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Definition
| RUNNING THE CPU AT A MULTIPLE OF THE BUS FREQUENCY |
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Definition
| A SPECIAL PROGRAM THAT TRANSLATES THE HIGHER-LEVEL LANGUAGE INTO MACHINE LANUGAGE BASE ON THE CPU's INSTRUCTION SET |
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Term
| COMPLEX INSTRUCTION SET COMPUTER (CISC) |
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Definition
| A CPU WITH A COMPLEX INSTRUCITON SET |
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Definition
| A CPU COMPONENTS THAT CONTROLS THE OVERALL OPERATION OF THE CCPU |
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Definition
| A CPU COMPONENT THAT DECODES INSTRUCTIONS AND DATA AND TRANSMITS THE DATA TO OTHER AREAS IN AN UNDERSTANDABLE FORMAT |
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Definition
| A BUS SYSTEM ARCHITECTURE IN WHICH ONE BUS CONNECTS TO THE MAIN MEMORY AND THE OTHER CONNECTS WITH THE L2 CACHE |
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Definition
| A TERM COINED BY INTEL TO DESCRIBE THE ENHANCED, THE SUPERSCALAR AND THE MULTIPLE BRANCH PREDICTION FEATURES ASSOCIATED WITH THE PENTIUM II PROCESSOR |
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Definition
| ANOTHER TERM FOR LOCAL BUS |
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Definition
| A SET OF BASIC COMMANDS THAT CONTROL THE PROCESSOR |
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Definition
| COMMANDS GIVEN TO THE PROCESSOR |
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Definition
| A CACHE CONTAINED WITHIN THE PROCESSOR THAT IS DESIGNED TO RUN AT THE PROCESSOR'S SPEED |
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Definition
| A CACHE MOUNTED OUTSIDE OF THE PROCESSORS. (NOTE:THE PENTIUM III INCORPORATES THE L2 IN THE PROCESSOR) |
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Definition
| THE CACHE MOUNTED ON THE MOTHERBOARD WHEN L1 AND L2 CACHES ARE INCORPORATED INTO THE CPU |
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Definition
A COMPONENTS OF THE CPU THAT IMPROVES THE PROCESSOR'S ABLITY TO PERFORM ADVANCED MATHEMATICAL CALCULATIONS |
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Definition
| A PROCESSOR WITH AN ADDITIONAL 56 COMMANDS THAT ENHANCE ITS ABILITES TO SUPPORT MULTMEDIA TECHNOLOGY |
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Term
| MULTIPLE BRANCH PREDICTION |
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Definition
| A TECHNIQUE THAT PREDICTS WHAT DATA ELEMENT WILL BE NEEDED NEXT, RATHER THAN WAITING FOR THRE NEXT COMMAND TO BE ISSUED |
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Definition
| FORCING A PROCESSOR TO OPERATE FASTER THAN ITS APPROVED SPEED |
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Definition
| THE PATTERN OF PINS ON A CPU |
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Definition
| THE ABLITY TO SELECT THE NUMBER OF CPU CORES TO APPLY TO A SOFTWARE APPLICATION |
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Definition
| CONTROLLING PORCESSOR FREQUENCY TO CONSERVE BATTERY LIFE AND PRODUCE LESS HEAT |
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Term
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Definition
| AN OPERATING MODE THAT SUPPORTS MULTITASKIN AND ALLOWS ACCESS TO MEMORY BEYOND THE 1 MB |
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Term
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Definition
| AN OPERATING MODE IN WHICH ONLY THE FIRST 1MB OF A SYSTEM'S RAM CAN BE ACCESSED. ALSO, AN OPERATIONG MODE IN WHICH THE 286 OR LATER PROCESSORS EMULATES AN 8088 OR 8086 PROCESSOR |
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Term
| REDUCED INSTRUCTION SET COMPUTER (RISC) |
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Definition
| A TYPE OF CPU ARCHITECTURE THAT IS DESIGNED WITH A FEWER NUMBER OF TRANSISTOR AND COMMANDS |
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Definition
| A CPU COMPONENT CONNTAINING MANY SEPARATE, SMALLER UNITS KNOWN AS REGISTERS |
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Definition
| SMALL POCKETS OF MEMORY WITHIN THE PROCESSOR THAT ARE USED TO TEMPORARILY STORE DATA BEING PROCESSED BY THE CPU |
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Definition
| EXECUTING TWO OR MORE THREADS AT THE SAME TIME |
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Definition
| PROCESSING MULTIIPLE INSTRUCITONS SIMULTANEOUSLY |
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Term
| SYSTEM MAMAGEMENT MODE (SMM) |
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Definition
| A STANDBY MODE DEVELOPED FOR LAPTOP COMPUTERS TO SAVE ELECTICAL ENERGY WHEN USING THE BATTERY |
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| PART OF A SOFTWARE PROGRAM THAT CAN BE EXECUTED INDEPENDENTLY OF THE ENTIRE PROGRAM |
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Definition
| AN OPERATIONAL MODE IN WHICH THE PROCESSOR CAN OPERATE SEVERAL REAL MODE PROGRAMS AT ONCE AND ACCESS MEMORY HIGHER THAT THE FIRST 1MB |
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Term
| ZERO INSERTION FORCE(ZIF) SOCKET |
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Definition
| A PROCESSOR SOCKET EQUIPPED WITH A LEVER TO ASSIST IN THE INSTALLATION OF THE CPU |
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